1. Field of the Invention
The present invention relates to a so-called QPSK (Quadrature Phase-Shift Keying) demodulator for a signal simultaneously transmitting two binary signals I and Q on two carriers having the same frequency but in phase quadrature.
2. Discussion of the Related Art
FIG. 1 schematically and partially shows a conventional QPSK demodulator used to demodulate signals transmitted by satellite. A channel filter 10 receives a signal S from a first demodulator generally integrated to the reception head of a dish aerial pan. Channel filter 10 provides a so-called intermediary frequency signal IF, carrying the signals modulated on a 479.5 MHz carrier. Signal IF is provided to two multipliers 12 and 13 which further receive, respectively, two signals cos and sin, in phase quadrature. The cos and sin signals are provided by an oscillator 15 operating at a fixed frequency as close as possible to the 479.5-MHz intermediary frequency.
The baseband outputs Im and Qm of multipliers 12 and 13 are provided to two respective low-pass filters 17 and 18 which themselves provide the two demodulated signals I and Q. Actually, this demodulation is only a rough demodulation, since the frequency of oscillator 15 never is exactly equal to the intermediary frequency. To correct the demodulation error and extract the binary values from signals I and Q, signals I and Q generally undergo a digital processing in a digital signal processor (DSP) 20. Previously, signals I and Q are processed by analog-to-digital converters 22. The frequency of signals I and Q can generally reach 30 MHz, whereby converters 22 are clocked by a clock of at least 60 MHz.
In many applications, converters 22 and processor 20 are integrated in a circuit distinct from that which performs the other functions, especially to limit interference between the digital and analog portions of the demodulator.
An object of the present invention is to provide a complete QPSK demodulator in an integrated circuit which can be adapted in a particularly simple way to some demodulators which do not require all the demodulation functions that the integrated circuit can perform.
To achieve this and other objects, the present invention provides a demodulator devised to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock of frequency smaller than the intermediary frequency, at least equal to the band width of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, xe2x88x921, 1, xe2x88x921, 1 . . . at the clock rate.
According to an embodiment of the present invention, the demodulator includes, in the path of the signal provided to one of the analog-to-digital converters, a clock change circuit.
According to an embodiment of the present invention, the demodulator includes, in the path of the signal provided by the other analog-to-digital converter, a filter of interpolation of one half clock period.
According to an embodiment of the present invention, the demodulator includes switches connected for, in a predetermined position, connecting two distinct signals to the two analog-to-digital converters, providing the same clock to the two converters, and continuously providing the two multipliers with value 1.